1. Field of the Invention
The present invention relates to an incrementer circuit, and is mainly devoted to an incrementer circuit which composes a part of the program counter circuit of a microcomputer constructed of MISFETs (insulated gate field-effect transistors).
2. Description of the Prior Art
As one of the circuits constituting the CPU (central processing unit) of a computer, there is the program counter circuit.
This circuit is necessary for sequentially designating program addresses, and is constructed and operated as will be explained hereunder.
FIG. 12 shows a block diagram of a program counter circuit. As is illustrated in the figure, this circuit is made up of a counter portion (incrementer circuit) 45, a memory portion 46 and gate portions 47 and 48. With this circuit, in the absence of a jump instruction, an address with 1 (one) added to an address which is stored in the memory portion 46 and which is an address presently under execution of a program is formed by the counter portion 45. It is passed through the gate circuit 47, and is stored in the memory portion 46 as a new address. In this manner, program addresses are caused to be sequentially advanced. On the other hand, in the presence of a jump instruction, the jump address is passed through the gate circuit 48 and is stored in the memory portion 46. Thereafter, until the next jump instruction is received, program addresses are caused to be advanced as above by the counter portion 45 on the basis of the jump address.
Depending on whether the jump instruction is present or not, only the input signal of one of the two gate circuits 47 and 48 is stored in the memory portion 46, and the input signal of the other is inhibited. That is, the above operation is carried out by controlling the gate signals G.sub.1 and G.sub.2 in a complementary manner.
For the program counter circuit, the following two systems have been proposed in the case of the general computers. In one of them, a flip-flop circuit is employed for the memory portion, a 1 (one) is added to the information stored in the flip-flop circuit by the incrementer circuit, and the result is again stored in the flip-flop circuit as new information.
In the other system, a special flip-flop circuit, for example, an R-S type flip-flop circuit, is used as the memory portion, and a carry circuit, for determining if the flip-flop circuit is inverted, is additionally provided. More specifically, as to each of n flip-flop stages for storing information containing n digits, whether or not the particular digit is inverted is determined by the carry circuit in dependence on stored information for digits lower than the digit.
With the former system, the flip-flop circuit is simple in arrangement, but the incrementer circuit is complicated. With the latter system, the flip-flop circuit is complicated in arrangement, and the carry circuit corresponding to the incrementer circuit is simple.
Where the program counter circuit is applied to the CPU of a microcomputer constructed of an MIS integrated circuit, the memory portion is not constructed of a flip-flop circuit and utilizes a part of a RAM (random access memory) space for such purposes as reducing the number of constituent elements. The former system described above has been chiefly adopted.
As the incrementer circuit, the one as shown in FIG. 13 has been commonly employed. As is illustrated in the figure, this circuit is composed of exclusive OR circuits and AND gate circuits. By way of example, where "1" is added to input information containing (n + 1) digits at a.sub.0 -a.sub.n, to obtain output information a.sub.0 '-a.sub.n ', the input signal a.sub.0 of the least significant digit and the information "1" are first applied to the exclusive OR circuit 49. When the input information of the digit a.sub.0 is "1", the output a.sub.0 ' of the exclusive OR circuit 49 becomes "1" .sym. "1" = "0". On the basis of a logical calculation "1" .sym. "1" = "0", the least significant digit becomes "0", which is coincident with the above result. When the input information a.sub.0 is "0", the output a.sub.0 ' becomes "1" .sym. "0" = "1" and it coincides with a logical calculation "1" .sym. "0" = "1".
As regards the second digit, the input information a.sub.1 of the digit is applied to one input of the exclusive OR circuit 50, while the input information a .sub.0 and the addition information "1" of the digit lower than the second digit are applied through the AND circuit 53 to the other input of the circuit 50. Accordingly, where the output of the AND circuit 53 is "1", that is, where a carry signal from the lower digit is present, the output a.sub.1 ' of the exclusive OR circuit 50 becomes the inverted signal a.sub.1 of the input information a.sub.1. Where the carry signal is absent, the output a.sub.1 ' becomes the input information a.sub.1 itself. That is to say, in the presence of the carry signal, when the input information a.sub.1 of the digit is "1", this information "1" has the carry information "1" added, to make the output information a.sub.1 '"0", while when the input information a.sub.1 is "0", this information "0" has the carry information "1" added, to make the output information a.sub.1 '"1". In the absence of the carry signal, the information to be added to the input information a.sub.1 of the digit becomes "0", so that the input information a.sub.1 is produced as the output information a.sub.1 ' without any change.
In the same way, circuits at the digits a.sub.2 to a.sub.n are constructed of exclusive OR circuits and AND circuits. At the digit a.sub.n, the AND circuit 55 has (n + 1) input information (which are not fully illustrated in the figure).
Each of the exclusive OR circuits 49-52 in the foregoing incrementer circuit is composed of NAND circuits 56 and 57 and an OR circuit 58 as shown in FIG. 14. In an MIS integrated circuit which is constructed with an inverter circuit as its fundamental logical circuit, each of the AND circuits 53-55 shown in FIG. 13 is composed of a NAND circuit and an inverter circuit, and the OR circuit 58 shown in FIG. 14 is composed of a NOR circuit and an inverter circuit. Accordingly, where, for example, the circuit of the digit a.sub.2 in FIG. 13 is constructed into an MIS integrated circuit, the circuit arrangement is as illustrated in FIG. 15. That is, the AND circuit 54 is composed of a 3-input NAND circuit 62 and an inverter circuit 61, while the OR circuit 58 is composed of a NOR circuit 60 and an inverter circuit 59.
A concrete example of the circuit arrangement is shown in FIG. 16. In order to form the parts 62, 57 and 56 in the figure as NAND circuits and to form the part 60 as a NOR circuit, positive logic must be adopted where MISFETs 63-79 are p-channel transistors, whereas negative logic must be adopted where they are n-channel transistors.
As is apparent from FIGS. 15 and 16, the circuit arrangement includes a comparatively large number of MISFETs, and a large number of logical steps. When it is constructed of an MIS integrated circuit, there are problems in the operating speed and the degree of integration.